Efficient HLS Implementation of Fast Linear Discriminant Analysis Classifier

Abstract

Linear discriminant analysis(LDA) classification is widely used in the current field of machine learning and data mining. However, its computational complexity tends to cause high processing latency when implemented on Field Programmable Gate Array (FPGA), especially for high dimensional data. This letter proposes a method to reduce computational complexity, which uses principal component analysis (PCA) to obtain the most representative characteristics of the original data for projection. Instead of the original data, the dimension reduced data obtained by the projection will be used for classification. Moreover, when there is only one main characteristic value, not only the matrix inversion operation is avoided, but also a large number of matrix multiplication operations are simplified. The implementation of the classifier on FPGA is realized using High Level Synthesis(HLS), which can effectively save hardware development time. The results show that the method has an encouraging performance in reducing the execution time of the algorithm on FPGA, while the accuracy of the classifier can also be guaranteed.