High Level Design of a Flexible PCA Hardware Accelerator Using a New Block-Streaming Method

Mohammad Amir Mansoori,Mario R Casu

doi:10.3390/electronics9030449

Abstract

Principal Component Analysis (PCA) is a technique for dimensionality reduction that is useful in removing redundant information in data for various applications such as Microwave Imaging (MI) and Hyperspectral Imaging (HI). The computational complexity of PCA has made the hardware acceleration of PCA an active research topic in recent years. Although the hardware design flow can be optimized using High Level Synthesis (HLS) tools, efficient high-performance solutions for complex embedded systems still require careful design. In this paper we propose a flexible PCA hardware accelerator in Field-Programmable Gate Arrays (FPGA) that we designed entirely in HLS. In order to make the internal PCA computations more efficient, a new block-streaming method is also introduced. Several HLS optimization strategies are adopted to create an efficient hardware. The flexibility of our design allows us to use it for different FPGA targets, with flexible input data dimensions, and it also lets us easily switch from a more accurate floating-point implementation to a higher speed fixed-point solution. The results show the efficiency of our design compared to state-of-the-art implementations on GPUs, many-core CPUs, and other FPGA approaches in terms of resource usage, execution time and power consumption.

Highlights

Principal Component Analysis (PCA) is a widely-used method for reducing dimensionality.It extracts from a set of observations the Principal Components (PCs) that correspond to the maximum variations in the data
In a preliminary version of this work [20], we proposed another High Level Synthesis (HLS)-based PCA accelerator to be used with flexible data dimensions and precision, but limited in terms of hardware target to a low-cost Zynq SoC and without the support for block-streaming needed to handle large data matrices and covariance matrices, which instead we show in this paper
We proposed a new hardware accelerator for the PCA algorithm on Field-Programmable Gate Arrays (FPGA) by introducing a new block-streaming method for computing the internal covariance matrix

Summary

Introduction

Principal Component Analysis (PCA) is a widely-used method for reducing dimensionality. It extracts from a set of observations the Principal Components (PCs) that correspond to the maximum variations in the data. By projecting the data on an orthogonal basis of vectors corresponding to the first few PCs obtained with the analysis and removing the other PCs, the data dimensions can be reduced without a significant loss of information. PCA can be used in various applications when there is redundant information in the data. In Microwave Imaging (MI), PCA is useful before image reconstruction to reduce data dimensions in microwave measurements [1,2,3]. In a recent work [4], PCA is used as a feature extraction step prior to tumor classification in MI-based breast cancer detection

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