Abstract

The enhancement of process, the feature size of device becomes smaller, and the deductions of power supply require the design of SRAM should be consummated. For the design of 6-T SRAM, although we have many methods to optimize it in order to overcome lots of challenges. But the smaller feature size and lower power supply will produce a decline in the performance of Static Noise Margin (SNM) and increase of leakage current. They also produce much more uncertain factors than before. To make matters worse, 6-T SRAM may not work properly. So a new structure with good design-for-yield (DFY) to work at lower supply voltage becomes more important. We have found a alternative structure, which we call it 8-T SRAM. And we can prove its performance is more suitable for the demand in the future SRAM design. But there is still no comprehensive method to optimize 8-T SRAM design, and we don't know whether its yield is acceptable or not. In this paper, we propose a comprehensive method for statistical 8-T SRAM design relying on an efficient combination of yield analysis and performance optimization. To the best of our knowledge, this is the first time that such a comprehensive method is applied to analyzing and optimizing the 8-T SRAM design with lower power supply.

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