Efficient Gate Capacitance and Current Modeling of High-k Gate Stacks

Abstract

Computationally efficient and accurate physically-based self-consistent compact models of CMOS gate-capacitance (Cg-Vg) and gate-current (Ig-Vg) for both ultra-thin SiO2 and high-k gate-stacks down to ~ 0.5 nm EOT are reviewed. The compact model produces results comparable to those obtained via computationally intense simulators. A modified Levenberg-Marquardt algorithm has been used in combination with these models to provide an efficient material and device parameter extraction capability. In a few seconds, parameters such as effective oxide thickness, surface substrate doping concentrations, flat-band voltages and poly-Si doping concentrations can be obtained from measured Cg-Vg, and physical thicknesses, band offsets, dielectric constants and tunneling masses for the gate-dielectrics can be extracted from measured Ig-Vg.