Efficient FPGA Implementation of a Digital Predistorter for Power Amplifier Linearization

Abstract

This paper presents a fixed point design and implementation of a low-complexity high-throughput digital predistorter (DPD) on FPGA. Based on the memory polynomial model, a parallel structure is proposed for the implementation of the DPD and the effects of the fixed-point implementation on the performance are analyzed employing fidelity metrics such as modulation error ratio and adjacent channel power ratio. According to this analysis, an optimized fixed-point hardware implementation of the proposed DPD with proper word lengths is presented. Besides some simplifications to the proposed structure, a number of effective modifications are proposed for clock enhancement. The improved clock frequency of the proposed implementation makes it a fit choice for application over communication signals with considerable bandwidth. The required hardware and the maximum clock rate corresponding to these modifications are evaluated and reported. The performance of the proposed DPD in linearization of an actual power amplifier (PA) is also experimentally evaluated, through application of an appropriate hardware setup. Experimental results show about 11 dB ACPR improvement in the PA output for a 128-QAM test signal. The moderate hardware resource requirement of the proposed high-throughput DPD is also verified through comparison with some remarkable works in the same area.