Efficient FDWT/IDWT hardware implementation with line-based and dual-scan image memory accesses

Abstract

Image compression is of a great importance in multimedia system applications because it drastically reduces bandwidth for transmission and memory storage. Image compression algorithm, like JPEG2000, utilizes the Forward Discrete Wavelet Transform (FDWT) and Inverse Discrete Wavelet Transform (IDWT). The main problems face by researchers in the hardware implementation of the FDWT/IDWT are storage memory, internal processing buffer and the limitation of the FPGA resources. Memory access method significantly affects the design architecture of FDWT/IDWT. The off-chip memory access consumes more power while the on-chip memory increases the hardware cost. In this paper, we propose an FDWT/IDWT architecture that is based on the line-based and dual-scan methods. Both architectures reduce the number of image memory accesses. The line-based architecture reduces the internal buffer by 2 × 0.5 × N where N is the dimension of image size. The implemented dual-scan architecture does not use any the internal memory. Both architectures were implemented on the Altera Cyclone II EP2C70F672C6 FPGA board and ran at frequency of 100 MHz.