Efficient dicing of silicon ingots for photovoltaic applications

Abstract

The global market for photovoltaic (PV) technology has grown a hundred times in the last 20 years, but its usage has been limited due to high cost. The PV industry requires the cutting of silicon ingots into wafers such that it minimizes kerf loss, allows slicing of large size (diameter) and ultra-thin wafers, provides crack free and highly finished surface on Si wafers. Also, considering the huge demand for Si wafers in PV applications, the dicing technology should maximize productivity while minimizing the cost. The existing abrasive based dicing methods can produce Si wafers of size 250-300 μm. However, there are enormous kerf losses and many other difficulties, which necessitate the development of new alternatives. In the recent past, wire-EDM (electric discharge machining) and plasma etching have been identified as potential alternatives. The wire-EDM uses electric discharge between low resistive Si ingot and conducting wire to melt and vaporize the ingot material. It uses a wire of size 100-200 μm normally, but the minimum wire size can be as small as 25-30 μm, which could reduce the kerf loss significantly. The process does not apply any cutting force on ingots and gives highly finished, crack free surface, irrespective of the ingot size. The process, however, produces localized contamination layer of thickness 10-35 μm, which can be removed either by polishing or by etching process. Furthermore, the hybrid machining yields even better quality surface than wire-EDM. Initial experimentation of Si wafer cutting by micro-wire-EDM has shown that cuts as small as 60 μm wide could be made easily by the process. This paper therefore critically reviews the performance of abrasive-based and emerging methods in dicing of Si ingots. It provides further inputs on the feasibility of the wire-EDM process in dicing of Si wafers based on the authors' experimental work.