Efficient algorithm and architecture for post-processor in HDTV

Abstract

To display high quality images on the monitor screen in HDTV, the processed image data must be converted into a form appropriate for real-time display. This paper presents the efficient algorithm and architecture for the post-processor, which has four functions. The first function is to remove the blocking effect in HDTV images, and the second is to convert the scan formats appropriate for the display. The third function is to convert the YUV format image signals into the RGB format signals. The final function is the /spl gamma/ correction for better quality images. To reduce the memory size, the memory is partitioned into many memory banks. Also, to improve the operation speed, a pipelined parallel architecture and a memory scheduling technique are adopted. Therefore this architecture is very fast and uses small size memory banks, and this makes it possible to realize a real-time signal processor.