Efficient A* Co-processor for Reconfigurable Gaming Devices

Abstract

Pathfinding algorithms are at the heart of most games, especially to fulfill increasingly demanding Artificial Intelligence and Level Design tasks. Recent smartphones and tablets are equipped with efficient Multi-Processing Systemson-Chip (MPSoC) devices, with demanding performance requirements and energy consumption constraints. While not primarily designed for gaming, such mobile machines are quickly climbing to the top of the list of preferred gaming devices, augmented at each new product iteration with stateof-the-art multimedia subsystems and co-processors. Therefore, this work aims at designing and evaluating an efficient A* pathfinding co-processor for reconfigurable gaming devices. The co-processor is designed using Xilinx High-Level Synthesis (HLS) compiler and is implemented in the programming logic of a Xilinx Ultrascale+ Field-Programmable Gate Array (FPGA) embedded with a 64-bit quad-core ARM Cortex-A53 MPSoC, dual-core Cortex-R5 real-time processors, and a Mali400 MP2 graphics processing unit. Extensive performance, circuit-area and energy consumption results shows that the coprocessor running at only 200MHz can efficiently find paths approximately four times faster than one ARM processor running at 1.2GHz for a set of pathfinding benchmarks based on artificial maps and commercial games such as StarCraft and Baldur’s Gate, paving the way for novel dedicated gaming co-processors. Moreover, the co-processor only requires about one third of the system’s total dynamic power.