Efficient 3-parallel polyphase odd length FIR filter using Brent Kung adder and Booth multiplier for VLSI applications

Abstract

In design and implementation of DSP processors reduction in power consumption and area optimization constitutes the primary criteria. Parallel Finite Impulse Response (FIR) filter is at the core of the design and implementation. In this paper, usage of FFA based 3-parallel polyphase FIR filter with optimized adder and multiplier in place of traditional adder and multiplier has been presented. Accordingly, FFA based 3-parallel polyphase odd length FIR filter using two different multipliers namely Vedic multiplier and Booth multiplier and three different adders namely Ripple carry adder, Carry lookahead adder, and Brent Kung adder has been proposed. FFA based 3-parallel polyphase FIR filter have been further implemented using different multipliers and adders and are then compared for various parameters. The proposed filters are designed on FPGA kit Artix-7 and are implemented using Xilinx vivado. The gain is both in terms of delay and area. Additionally, low power consumption and delay reduction in the Booth multiplier as well as Brent Kung adder make it highly preferable for designing of the parallel FIR filter for low power and small chip area VLSI applications.