Design and FPGA Implementation of High-speed Parallel FIR Filters

Abstract

This paper proposes a novel design method of parallel Finite Impulse Response (FIR) filter, which structure is parallel transposed. It can increase the running speed by M times compared with the serial FIR filter, where the M is the number of sub-filters, and the parallel FIR filter only introduces very small delay. Firstly the theoretical foundation of parallel FIR filters is analyzed. An example of the floating point parallel transposed FIR band-pass filter is given to verify the algorithm. Then a parallel transposed FIR band-pass filter is designed, which has optimum fixed point coefficients. Finally the fixed point of this filter is implemented in Xilinx's Virtex-6 Field Programmable Gate Array (FPGA). According to the simulation results, this filter has smaller resource consumption and its sampling rate up to 1.2GHz.