Abstract
In this paper, the output power, phase response, and drain efficiency of a class-E power amplifier with shunt capacitance, composed of nonlinear and linear capacitance, is analyzed to manifest the cause of efficiency degradation at low drain dc supply voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dc</sub> ). Analysis also shows that the drain efficiency at low <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dc</sub> can be improved by reducing the on-duty ratio; a simple efficiency enhancement method with gate dc bias voltage adjustment is proposed. Numerical and simulated results are given in comparison to show the validity of the theoretical analysis and the proposed method. An experimental class-E amplifier, designed at 100 MHz, is measured; the drain efficiency declines by 14% at 0.8 V <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dc</sub> compared to the highest efficiency. With the optimized gate dc bias voltage, the 7.5% drain efficiency improvements and 9.26-dB dynamic range extension are measured at low <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dc</sub> in the experiment.
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