Abstract
The p +-gridded MNOS capacitor was fabricated to facilitate the study of the effects of Write/Erase cycling and of varying the processing parameters on the interface-state density in an MNOS nonvolatile memory device. A model is derived for this device, which enables the extraction of the device parameters using the quasi-static C− V (QSCV) technique. The distribution of the interface-state density across the forbidden energy gap of silicon was deduced from QSCV measurements. Interface-state density minima between 1.8 × 10 11 and 9.1 × 10 11 eV −1 cm −2 near the silicon midgap were obtained. The effects of processing variations on the Si/SiO 2 interface-state density distribution and the retention characteristics of the MNOS were studied.
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