Effects of Thinned Multi-Stacked Wafer Thickness on Stress Distribution in the Wafer-on-a-Wafer (WOW) Structure

Abstract

AbstractIn the trough silicon via (TSV) structure for 3-dimensional integration (3DI), large thermal-mechanical stress acts in the TSV caused by the mismatch in thermal expansion coefficient (CTE) of the TSV materials. In this study, the stress of multi-stacked thin silicon wafers composed of copper TSV and copper/low-k BEOL structure was analyzed by the finite element method (FEM), aiming to reduce the stress of TSV of 3D-IC. The results of sensitivity analysis using design of experiment (DOE) indicated that the thickness of the silicon and adhesive layer are the key factors for the structural integration of TSV design.