Effects of thicknesses of Si/Al/Si composite films and annealing temperature on metal-induced si crystallization efficiency, voids, and electrical properties

Abstract

Specimens with amorphous silicon (a-Si)/aluminum (Al)/a-Si composite film were prepared to evaluate the effects of the thickness variation of these three film thicknesses and annealing temperature on the Al-induced crystallization (AIC) efficiency of a-Si and the quantity of stress-induced voids. These thin films were arranged in sandwich form for the purpose to improve the AIC efficiency via Al diffusions into the two adjacent Si films and reduce the defect of voids. The PC parameter is defined as the product of the crystalline fraction and the grain size of Si crystallization, and R* is a parameter defined as the area fraction of nanovoids in a unit area. The influence of these two parameters on Si crystallization is governed by the annealing temperature (T) and thus the stress change, σf –σan (σf : stress after annealing; σan : stress during annealing), and the thickness ratio, tAl/(tSi1+tSi3) (tAl: Al film thickness; tSi1, tSi3: thicknesses of the 1st and 3rd layers (a-Si), respectively). Si crystallization doesn't happen when tAl/(tSi1+tSi3) is less than 4% and the annealing temperature is lower than 600°C. The sandwich structure contains voids if tAl/(tSi1+tSi3) is greater than 6% and the negative stress change (σf –σan) is lower than −500MPa. A rise in σf –σan decreases R* but increases PC, if the specimens contain voids. The carrier mobility of specimen is elevated by increasing the negative σf –σan or the PC value. At a fixed PC, the carrier mobility of the specimen without forming voids is higher than that of the specimen with voids. The electrical conductivity of specimen increases with decreasing specimen band gap. Appropriate choices in the film thicknesses of the sandwich structure and the annealing temperature can increase the Hall carrier mobility and electrical conductivity to be much higher than those of the Al/a-Si structure.