Effects of Substrate Thinning on the Properties of Quadruple Well CMOS MAPS

Abstract

The chip prototype Apsel4well, including monolithic active pixel sensor (MAPS) test structures, has been designed for vertexing applications requiring a fast and low material silicon vertex tracker. The chip is fabricated in a 180 nm CMOS process called INMAPS, featuring a quadruple well and a high resistivity epitaxial layer option. The main advantage with this approach lies in the chance of increasing the in-pixel intelligence as compared to standard three transistor MAPS schemes. Moreover, the presence of the quadruple well and of the high resistivity epitaxial layer leads to better charge collection performance and radiation resistance. Different samples of the Apsel4well chip have been thinned down to about 25 μm and 50 μm. This minimization of the material can further improve the tracker performance virtually with no charge signal loss. At the beginning, this paper focuses on the results from charge collection TCAD simulations of the Apsel4well pixel structure performed at different thicknesses and substrate bias voltages. Later on, results from measurements relevant to the thinned chips both in terms of analog front-end channel performance and charge collection properties will be shown and compared to those from non-thinned chips.