Effects of source-drain underlaps on the performance of silicon nanowire on insulator transistors

Khairul Alam,Sishir Bhowmick

doi:10.5101/nml.v2i2.p83-88

Abstract

The effects of source-drain underlaps on the performance of a top gate silicon nanowire on insulator transistor are studied using a three dimensional (3D) self-consistent Poisson-Schrodinger quantum simulation. Voltage-controlled tunnel barrier is the device transport physics. The off current, the on/off current ratio, and the inverse subthreshold slope are improved while the on current is degraded with underlap. The physics behind this behavior is the modulation of a tunnel barrier with underlap. The underlap primarily affects the tunneling component of drain current. About 50% contribution to the gate capacitance comes from the fringing electric fields emanating from the gate metal to the source and drain. The gate capacitance reduces with underlap, which should reduce the intrinsic switching delay and increase the intrinsic cut-off frequency. However, both the on current and the transconductance reduce with underlap, and the consequence is the increase of delay and the reduction of cut-off frequency.

Highlights

Scaling the transistor sizes has made significant improvement in the cost effectiveness and performance of integrated circuit over the last few decades
The scaling of bulk silicon MOSFETs has been facilitated by introducing the device structures with source-drain underlaps [8]
We study the effects of source-drain underlaps on device performance, namely the off current, the on current, the inverse subthreshold slope, S, the gate capacitance, Cg, the intrinsic switching delay, WS, and the intrinsic cut-off frequency, fT, of a top gate silicon nanowire on insulator transistor by selfconsistently solving the Poisson's and Schrodinger's equations

Summary

DEVICE STRUCTURE

The silicon nanowire is placed on a thick oxide layer tox-sub. The gate oxide tox is grown on the nanowire. A gate metal of length Lg is deposited on gate oxide and the exposed regions on both sides of the gate metal are covered by oxide tox-ex. The nanowire under the gate region and the underlaps Lu between the gate and the n-type doped source and drain extension Lex are undoped. The gate length Lg is 10 nm and the gate oxide thickness tox is 1 nm. The substrate oxide, the gate oxide, and the extended oxide are SiO2 with a dielectric constant value of 3.9. The gate metal is assumed to have the same work function value as the nanowire has. The Lex value of 20 nm, the tox-sub value of 5 nm, and the tox-ex value of 5 nm are used for Poisson solver so that the fringing electric fields are treated correctly

SIMULATION MODEL

SIMULATION RESULTS

CONCLUSION