Effects of gate length on the performance of a top gate silicon nanowire on insulator (SOI) transistor

Abstract

The effects of gate length Lg on the performance of a top gate silicon nanowire on insulator transistor are studied using three dimensional quantum simulation. From the study it is found that the inverse subthreshold slope and on/off current ratio are very sensitive to gate length. Significant improvement in subthreshold slope and on/off current ratio can be achieved using relatively longer gate with thin gate oxide. This improvement in the subthreshold region is due to better control of channel potential with longer gate. As a result of that the tunneling current through the conduction band is significantly suppressed in the subthreshold regime and there is an improvement in the subthreshold slope and on/off current ratio. Performance metrics such as transconductance gm, intrinsic switching delay tauS and unity current gain frequency fT of the device are also calculated and it is found that the on state performance of the device degrades with longer gate as all three parameters degrade with increased gate length.