Abstract
Intrinsic fluctuations in threshold voltage, subthreshold swing, saturation drain current and subthreshold leakage of ultra-small-geometry MOSFETs due to random placement of dopant atoms in the channel are examined using novel physical models and a Monte-Carlo simulator. These fluctuations are shown to pose fundamental barriers to the scaling of supply voltage and channel length and thus, to the minimization of power dissipation in multi-billion transistor chips of the future. In particular, using the device technology and the level of integration projections of the National Technology Roadmap for Semiconductors for the next 15 years, standard-maximum deviations of threshold voltage, drive current, subthreshold swing and subthreshold leakage are shown to escalate to 40-600 mV, 10-100%, 2-20 mV/dec. and 10-10/sup 8/%, respectively, in the 0.07 /spl mu/m, 0.9 V CMOS technology generation with 1.3-64 billion transistors on a chip. While these limits can be transcended to some degree by selecting optimal transistor width values larger than the channel length, the associated penalties in dynamic and static power, and in packing density demand novel MOSFET designs aimed at minimizing these fluctuations.
Published Version
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call