Abstract
This paper reports the effects of post-deposition rapid thermal annealing on the electrical characteristics of chemical vapor deposited (CVD) Ta/sub 2/O/sub 5/ (/spl sim/10 nm) on NH/sub 3/-nitrided polycrystalline silicon (poly-Si) storage electrodes for stacked DRAM applications. Three different post-deposition annealing conditions are compared: a) 800/spl deg/C rapid thermal O/sub 2/ annealing (RTO) for 20 sec followed by rapid thermal N/sub 2/ annealing (RTA) for 40 sec, b) 800/spl deg/C RTO for 60 sec and c) 900/spl deg/C RTO for 60 see. Results show that an increase in RTO temperature and time decreases leakage current at the cost of capacitance. However, over-reoxidation induces thicker oxynitride formation at the Ta/sub 2/O/sub 5//poly-Si interface, resulting in the worst time-dependent dielectric breakdown (TDDB) characteristics. >
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