Effects of PCB power layouts design on switching transient performance of SiC MOSFETs

Abstract

This paper investigates the effects of Printed Circuit Board (PCB) layouts design of power stage on the switching transient performance of SiC MOSFETs-based Bidirectional Switching Power Pole (BSPP). SiC MOSFETs have compelling merits such as low power losses, high breakdown voltage, high thermal conductivity, high operating temperature capabilities, and excellent reverse recovery characteristics. To realize those features, it is challenging to design PCB layers for the power stage with low parasitic inductance to achieve high switching speed operation with an acceptable amount of ringing and overshoot in the switching transient waveforms. Therefore, this work introduced critical PCB design keys to achieving low parasitic inductance as well as symmetrical switching transient performance for both high and low side SiC MOSFETs based BSPP. A broad coupled traces method is used to design the PCB power traces with a minimum parasitic inductance for given geometric dimensions. Mathematical formulas are used to calculate the parasitic inductance of the PCB prototypes. The formulas purely depend on the geometric dimensions of the PCB layers and the thermal expansion coefficient of the substrate material. Cadence simulation tools are used to verify the parasitic inductance calculations of the experimental PCB prototypes by comparing both experimental and simulation switching transient performances.