Effects of parasitic capacitance on both static and dynamic electrical characteristics of back-gated two-dimensional semiconductor negative-capacitance field-effect transistors

Abstract

Negative-capacitance field-effect transistors (NC-FETs) are a promising candidate for future low-power Internet of Things (IoT) applications. In this work, a unified analytical drain-current model for back-gated two-dimensional (2D) NC-FETs has been proposed for both static and dynamic simulations, and this model is calibrated to experimental data. Effects of parasitic capacitance on both the static and dynamic electrical characteristics of back-gated 2D NC-FETs are investigated systematically on the basis of the model. It is found that parasitic capacitance contributes to the reduction in subthreshold swing but leads to a larger dynamic hysteresis. Thus, a balance between both should be carefully taken into account.