Influence of device architecture on the performance of negative capacitance MFMIS transistors

Abstract

We report a comparative analysis of the performance of negative capacitance field-effect transistors (NCFETs) with single gate, double gate, tri-gate (FinFET) and gate-all-around (GAA) device architectures, using TCAD simulations. Metal-ferroelectric-metal-insulator-semiconductor (MFMIS) structure is chosen for all NCFET devices. The NC behavior is attributed to the ferroelectric (FE) layer introduced into the gate stack of these devices. With aluminum doped hafnium oxide as the FE, electrical characteristics of NCFETs, with 40 nm or equivalent gate length, were simulated by solving a combination of Landau-Khalatnikov (LK) equation and metal oxide semiconductor field-effect transistor (MOSFET) equations. At a drain voltage, VD = 50 mV, NC-FinFET and NC-GAAFET achieve 45% and 67.5% reduction in sub-threshold swing (SS), respectively, compared to baseline devices, without any NC effect. In addition to improving sub-threshold performance, NCFETs have also shown higher ION/IOFF ratio than baseline devices for all device architectures. By tuning the thickness of the FE material, we have demonstrated capacitance matching, between FE and MOS capacitances, for non-hysteretic operation in NC-FinFET and NC-GAAFET. Matching FE and MOS capacitances allow for maximum NC effect. Results obtained from our TCAD simulations are consistent with reported experimental data and could provide useful insights into the design, operation and performance improvement of next generation NCFET devices.