Abstract
This paper presents a fabless design approach focusing on the impact of heterostructure design on the performance of low voltage GaN power HEMTs. Compared to the standard high voltage design process, low voltage design (<100 V) comes with a unique set of challenges especially concerning breakdown rules. Low voltage simulations reveal less dependence on vertical leakage current and substrate breakdown compared to high voltage designs, and more reliance on buffer leakage and punch-through as the dominant factors leading to breakdown. To analyze the impact of heterostructure design on the device performance, optimization curves are presented for breakdown voltage, on-state resistance, and gate charge. Simulations are performed in Sentaurus TCAD and correlated to known existing experimental results where possible. Trends are presented for the optimization of the channel layer thickness, barrier layer thickness and molar fraction, and impact of an AlN interlayer.
Published Version
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call