Abstract
Fabrication techniques used in processing cadmium telluride (CdTe) solar cell devices have been shown to introduce copper (Cu) into the cell structure. In fact, an accumulation of Cu in the cadmium sulfide (CdS) region has been seen, especially after back-contact processing. However, exactly how the presence of Cu near the device junction affects performance has yet to be determined. This study explores how CdS films are affected by Cu diffusion from a metallic layer and how these Cu-diffused layers (CdS:Cu) change the properties of thin-film CdS∕CdTe devices. Spectrophotometric analysis shows the optical bandgap of CdS films was 2.31eV following thermal diffusion of a 50Å Cu layer, compared to 2.43eV for CdS films that did not contain Cu. Characterization of the CdS:Cu films using grazing incidence x-ray diffraction (GIXRD) also produced noticeable shifts in the CdS peaks, likely due to Cu incorporation in the films. GIXRD, supported by Auger electron spectroscopy data, indicate that a Cu gradient is present in the CdS films as a result of the Cu treatments. Devices were completed using the CdS:Cu films, and the resulting performance was compared with standard CdS∕CdTe devices (i.e., no Cu evaporated at the interface). Standard devices had an open-circuit voltage (Voc) of 825mV, short-circuit current (Jsc) of 21mA∕cm2, fill factor (FF) of 64.2%, and efficiency (%η) of 11.1%. A similar device stressed for 900h had a Voc of 726mV, Jsc of 21mA∕cm2, FF of 29.2%, and efficiency of 6.9%. The device with a 10Å Cu layer diffused into the CdS (unstressed) had a Voc of 651mV, Jsc of 20.2mA∕cm2, FF of 44.2%, and efficiency of 5.8%. Similar trends in the performance parameters are seen between the stressed cell and the cell containing CdS:Cu. Modeled quantum efficiency (QE) curves for CdTe devices showed a reduction and shifting of the QE response near 500nm as the bandgap of the CdS is shifted to lower energy. This is consistent with trends in the QE curves, as a standard CdS∕CdTe device goes from an unstressed to a stressed state. The presence of Cu at the interface, perhaps incorporated in the CdS layer, may help explain the degradation seen in standard CdTe devices.
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More From: Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena
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