Effects of (0.01Ni-PVA) interlayer, interface traps (Dit), and series resistance (Rs) on the conduction mechanisms(CMs) in the Au/n-Si (MS) structures at room temperature

Abstract

In order to determine effects of interlayer, Dit, and Rs on the CMs, both Au/n-Si and Au/(0.01Ni-PVA)/n-Si (MPS) structures were fabricated on the n-Si wafer and their electrical parameters were extracted from the current-voltage (I-V) and capacitance-voltage (C-V) measurements. The ideality factor (n), zero-bias barrier height (ΦBo), rectifying rate (RR at ±5V), Rs, shunt resistances (Rsh), and density of Dit (at 0.40eV) values were found from the I-V data as 1.944, 0.733 eV, 3.50×103, 64.8 , 0.23 M, 1.62x1013 eV-1cm-2 for MS and 1.533, 0.818 eV, 1.15×107, 5.0 , 57.5 M, 8.82x1012 eV-1cm-2 for MPS. Fermi energy (EF), barrier height (ΦB(C-V)), depletion-layer width (WD) values were obtained from the C-V data as 0.239 eV, 0.812 eV, 1.14x10-4 cm for MS and 0.233 eV, 0.888 eV, 9.31x10-5 cm for MPS. These results indicated that the MPS structure has lower Rs, Dit, leakage current and higher RR, Rsh, BH compared with MS and so this interlayer can be successfully used instead of conventional insulator interlayer. The Ln(I)-Ln(V) plot at forward-bias region has three linear parts corresponding to the low, intermediate, and higher voltages. In these regions; conduction mechanism (CM) is governed by ohmic, trap charge-limited current (TCLC) and space charge-limited current (SCLC), respectively.