Effectiveness of potting methods and underfills on the enhancement of survivability of fine pitch electronics at 25,000g shock loads

Abstract

Surface mount BGA electronic components with smaller footprints were increasingly used in recent years due to their ability to achieve miniaturized form-factors without loss of functional attributes. The reliability characterization of these electronics under harsh environments applications is new. Electronics in military and aerospace applications may be subjected to high-g. Surface mount BGA solder joints may not survive due to the large strains experienced at high-g accelerations. In order to increase the drop performance of these electronics package reinforcements like underfilling and epoxy potting are used. The epoxy potting absorbs the high-g shock forces and transmits reduced amount onto the package solder joints. Not a lot of research was found in the literature regarding the selection and use of epoxy potting compounds on the reliability of fine pitch electronics under mechanical shock loads. In this paper, a circular PCB with an annular hole assembled with CTBGA and CVBGA components 0.5mm and 0.4mm respectively was studied using underfill and epoxy potting reinforcements under mechanical shock of 25,000g. The test board configuration is similar to JEDEC JESD22-B111, face down and constrained via four screws. The survivability and strain distribution is different as JEDEC standard is a rectangular board and tested at 1,500g shock. Three potting compound systems were studied in this work. Potting compound, A is a harder material, compound C is a softer material. Potting compound B has hardness range in between that of A and C. All the potting configurations have Lord Thermo set ME531 underfill reinforced beneath the packages. The survivability of the components for all the potting configurations is assessed by subjecting to high-g mechanical shock of 25,000g, 0.08ms shock pulse and recording the drops to failure for each component. The transient event was continuously monitored for continuity using high-speed data acquisition system. Two high-speed cameras operating at 8,200fps were used to capture the high-g shock event. 3D digital image correlation (DIC) was employed to characterize the full-field strain distributions of the PCB. The shock survivability of these configurations of the test vehicle was reported. Finite element model predictions were performed to characterize the peak displacement and solder-joint interconnect strains and compared with the experimental results.