Abstract
In this work, it was demonstrated that the Fermi level pinning in poly-Si/HfO2 can be effectively suppressed by using poly-SiGe gate. Threshold voltage of -1.02 V in poly-Si/HfO2 PFET was tuned to -0.81 V in poly-Si/Al2O3/HfO2, and further reduced to -0.49 V in poly-Si/poly-SiGe/Al2O3/HfO2. At the same time, Vth of 0.3 V for NFET was achieved in this poly-SiGe gate stack. Moreover, Vth stability was remarkably improved by using poly-SiGe gate and Al2O3 capping layer. The improvements shown in this poly-SiGe gate stack could be due to the suppressed formation of oxygen vacancies
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
