Effective suppression of Fermi level pinning in polycrystalline-silicon/high-k gate stack by using polycrystalline-silicon-germanium gate electrode

Abstract

In this study, the crucial issue of unacceptably high threshold voltage (Vth) induced by Fermi level pinning in poly-Si/high-k complementary metal-oxide-semiconductor field-effect transistor (MOSFET) was effectively suppressed by inserting a poly-SiGe gate electrode. The Vth of −1.02V in poly-Si∕HfO2 p-channel MOSFET was tuned to −0.81V in poly-Si∕Al2O3∕HfO2 and further reduced to −0.49V in poly-Si/poly-SiGe∕Al2O3∕HfO2 gate stack. Meanwhile, the Vth of 0.3V was achieved in the n-channel MOSFET with the poly-SiGe gate. Moreover, transconductance and Vth stability in the MOSFETs with poly-SiGe gate were remarkably improved compared to poly-Si∕HfO2 and poly-Si∕Al2O3∕HfO2 devices. The low Vth and good Vth stability observed in the devices with poly-SiGe gate may be mainly attributed to the suppressed formation of oxygen vacancies in high-k gate dielectric, which is commonly believed to cause the Fermi level pinning effect in poly-Si/high-k device.