Effective Low Power ALU Design with Incorporation of MWCNTB On-chip Interconnects

Abstract

Rigorous technology scaling results in embedding billions of transistors and interconnects on to a VLSI chip. This leads to high speed operation and more functionality in integrated circuits (ICs). However there is trade-off between speed and power in VLSI designs. At submicron technology nodes high power consumption becomes a challenging deal. It has been observed from literature that majority of the power dissipation happens in processing elements. One such basic operational component of any processor is arithmetic logic unit (ALU). This unit is designed with the help of combinational digital circuits to perform different arithmetic and logic operations. Data registers are used to hold the operands and result of ALU operation. Hence, for low power application ICs power dissipation at ALU, data registers and interconnections between them need to be taken care. For this purpose this research work has focused on implementing a low power ALU system using graphene based device and interconnects. Carbon nanotube field effect transistors (CNTFETs) are used to design basic logic gates that reduce power consumption of the system while multiwall carbon nanotube bundle (MWCNTB) interconnects are incorporated in connection between data registers that helps to increase speed of the system. 8-bit ALU, and data registers are designed using bottom–up approach, in which each system block is implemented using basic digital circuit. For validation purpose simulated results are compared with CMOS based ALU system. Experimentation is carried out at 22nm technology node. It is speculated from this work that CNTFET are good alternative for CMOS based transistors for low power application as well as higher speed.