Abstract
This paper presents a study of the nucleation process for W Chemical Vapor Deposition (CVD). The nucleation layer was obtained by reduction of WF 6 by SiH 4 and H 2. This double reduction had proved to have a large latitude regarding fluorine attack of the glue layer. High WF 6 flows could then be investigated and process parameters controlling the step coverage were determined. Electrical performance within a 0.25 μm CMOS interconnects scheme using a collimated PVD glue layer was investigated. The W nucleation layer proved to constitute a barrier layer against fluorine diffusion at the bottom of vias during via fill processing. Thus, a high step coverage W nucleation process extends the TiN barrier efficiency to a higher via aspect ratio.
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