Abstract
The relationship between the pinhole density in silicon nitride layers deposited on oxide-silicon structures and etching in buffered hydrofluoric acid is investigated in relation to the cooling down rate after Si3N4 deposition and subsequent annealing conditions. Si3N4 layers were deposited using a high temperature atmospheric pressure chemical vapor deposition technique on SiO2 patterned silicon substrates additionally covered with a thin SiO2 layer. Average numbers of pinholes per chip, as function of etch time, are presented both for differently treated wafers and for the specific locations on chips. The phenomenon is attributed to the preferential etching of Si3N4 in locations under stress.
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