Effect of the back bias on the analog performance of standard FD and UTBB transistors-based self-cascode structures

Abstract

This work demonstrates that active back biasing can improve significantly the analog performance of two-transistors self-cascode structures. The study was performed by applying both standard and UTBB fully depleted (FD) SOI MOSFETs to the structures and has shown that a voltage gain improvement of about 7 dB is obtained when a forward back bias is applied to the drain-sided transistor of standard FD devices-based structure. In the case of UTBB transistors, an improvement larger than 5 dB of the output voltage gain is shown depending on the back bias applied to both n- or p-type devices. Finally, it is shown that the mirroring precision of current mirrors composed by SC structures can be more than 20% better than the one composed by single devices and the improvement is better when adequate back bias is applied.