Use of back gate bias to enhance the analog performance of planar FD and UTBB SOI transistors-based self-cascode structures

Rodrigo T Doria,Marcelo A Pavanello,Renan Trevisoli,Denis Flandre,Michelly De Souza

doi:10.1109/sbmicro.2015.7298134

Use of back gate bias to enhance the analog performance of planar FD and UTBB SOI transistors-based self-cascode structures

Rodrigo T Doria, Marcelo A Pavanello + Show 3 more

https://doi.org/10.1109/sbmicro.2015.7298134

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Publication Date: Aug 1, 2015

Citations: 3

Affiliation: Centro Universitário da FEI, Université Catholique de Louvain

#Back Bias #Reverse Back Bias + Show 8 more

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Abstract

This paper reports, for the first time, the use of back gate bias to improve the intrinsic voltage gain of self-cascode structures composed by planar FD and UTBB SOI MOSFETs. It is shown a voltage gain improvement larger than 10 dB when either a forward back bias is applied to the drain-side transistor or a reverse back bias is applied to the source side device.

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