Effect of the Active Layer on Carbon Nanotube-Based Cells for Yield Analysis

Abstract

Carbon Nanotube Field Effect Transistor (CNTFET)--based technologies become more and more a concurrent alternative to Metal Oxide Semiconductor Field Effect Transistors (MOSFET) technologies. In contrast to a MOSFET technology, the active layer of a CNTFET technology is not a regular silicon film with homogeneous doping and rectangular dimensions, but an array of mostly aligned carbon nanotubes (CNTs). The quality of this active layer, which depends on various technology process parameters, is expressed by parameters such as CNT alignment and array density. These parameters affect the electrical properties of the logic cells placed on top of the active layer and hence the overall CNTFET circuit yield. Although not all parameters in CNT fabrication process can be fully controlled, designers still need to assure a very high yield of their cell layouts, that is, a high reproducibility of the electrical characteristics to achieve a reasonable manufacturing yield for the entire chip. In this work we close the gap between CNTFET process fabrication and circuit design by presenting a novel accurate model for active layers in CNTFET--based technologies. Our model enables the designers to obtain technology--dependent driver strength of the custom cell layouts under realistic conditions. The new model can also be used to extract and evaluate CNTFET Design for Manufacturing (DfM) and Design for Robustness (DfR) design rules, and provide feedback to adjust process technology parameters to achieve desirable functional yield.