Effect of strained Ge-based NMOSFETs with Ge0.93Si0.07 stressors on device layout

Abstract

This research proposes a germanium (Ge)-based n-channel MOSFET with Ge0.93Si0.07 S/D stressor. A simulation technique is utilized to understand the layout effect of shallow trench isolation (STI) length, gate width, dummy active of diffusion (OD) length, and extended poly width on stress distribution in a channel region. Stress distribution in a channel region was simulated by ANSYS software based on finite element analysis. Furthermore, carrier mobility gain was evaluated by a second-order piezoresistance model. The piezoresistance coefficient of Ge nMOSFET varies from that of Si nMOSFET. The piezoresistance coefficient shows that longitudinal and transverse stresses are the dominant factors affecting the change in electron mobility in the channel region. For Ge-based nMOSFET, longitudinal stress tends to be tensile, whereas transverse stress tends to be compressive. Stress along channel length becomes more tensile when STI length decreases. By contrast, stress along the channel width becomes more compressive when gate width or extended poly width decreases. Electron mobility in Ge-based nMOSFET could be enhanced under the aforementioned conditions. The enhanced electron mobility becomes more significant as the device combines with a contact etching stop layer stressor. Moreover, the mobility can be improved by changing the STI length, gate width, dummy OD length, or extended poly width. This investigation systematically analyzed the relationship between layout factor and stress distribution.