Effect of Silicon Thickness and Surface Passivation on the Characteristics of Amorphous Silicon thin Film Transistors

Abstract

Passivation of the back channel of thin film a-Si:H FETs is discussed. A one-dimensional model is used to predict the effect of back surface interface state density on the threshold voltage and subthreshold slope. A passivation method is described which results in a very high density of interface states. Two methods based on dual gate FETs are used to determine the interface state density. The principal effect of this method of passivation is to make the threshold voltage and subthreshold slope dependent on silicon thickness. This dependence is verified experimentally. For silicon > 150 nm, the dependence is weak. Variations in the deposition temperature of the passivation dielectric and the use of SiN x and SiO x are shown to have only a small effect.