Effect of SIIS on work function of self-aligned PtSi FUSI metal-gated capacitors

Abstract

A novel self-aligned fully silicided (FUSI) gate process for the integration of platinum monosilicide (PtSi) as a metal gate for pMOS applications is presented. It is shown that during Pt silicidation at elevated temperatures in oxygen ambient, a thin continuous SiO/sub 2/ film grows along the Pt-silicide outer surface that effectively protects the FUSI structures during the selective metal wet etch. PtSi FUSI MOS capacitors were fabricated with the new process and electrically characterized. The PtSi work function /spl Phi//sub m/ was extracted as 4.90 /spl plusmn/ 0.02 eV on SiO/sub 2/ and 4.83 /spl plusmn/ 0.05 eV on HfSiO gate dielectric. The /spl Phi//sub m/ difference is attributed to a Fermi-level pinning at the gate/HfSiO dielectric interface. The effect of implanted dopants prior to the FUSI process on the PtSi /spl Phi//sub m/ on SiO/sub 2/ gate dielectric is also addressed. Dopants investigated (As, P, and Sb) resulted in a work function reduction with respect to undoped PtSi, with the largest work function shift /spl Delta//spl Phi//sub m/ obtained for Sb. The correlation between /spl Delta//spl Phi//sub m/ and SIIS at the PtSi/dielectric interface is discussed in terms of first-principle simulations, taking into consideration impurity atom size and the change in surface dipole in a PtSi/impurity/vacuum system.