Effect of Post Deposition Annealing on ALD-ZrO2/SiON Gate Stacks for Advanced CMOS Technology

Abstract

To meet the existing challenges associated with gate leakage current and scaling beyond 22 nm node, we report the fabrication of 8.46 nm thin ALD-ZrO2 film on silicon substrate with ~ 5.43 nm SiON as interfacial layer. Electrical characterizations such as capacitance-voltage and current-voltage measurements reveal that the post deposition annealing (PDA) of ZrO2 in NH3 ambient results in improving various performance parameters such as leakage current density (92% decrease), effective oxide thickness (~22% decrease) and dielectric constant (~32% increase) when compared to PDA in N2 ambient. The surface roughness for N2 and NH3 annealed ZrO2 samples studied using AFM were found to be 0.4949 nm and 0.1385 nm respectively; thereby showing 72% decrease in surface roughness for NH3 annealed samples. The thicknesses of the grown films were corroborated by Ellipsometry and FESEM while the structural analysis was carried out using FTIR technique. The results demonstrate that post deposition annealing of ZrO2 film in NH3 ambient at 5000 C using rapid thermal processing (RTP) gives reduced EOT (~ 1.7 nm), increased K (~30) along with the suppressed off-state leakage current density (2.1× 10-9 A/cm2) and this performance enhancement is attributed to the effective replacement of oxygen by nitrogen atom to form a thermally stable phase of ZrON. Some of the important results obtained from the present work has been exemplified in the figure below. Keywords: Post depositionannealing (PDA); Zirconium oxide (ZrO2); leakage current density (J); effective oxide thickness (EOT); high- K dielectrics. Figure 1