Argon Annealed ALD-ZrO2/SiON Gate Stack for Advanced CMOS Devices

Abstract

We report on the fabrication of ultra-thin silicon oxynitride (SiON ~ 5.34 nm) as sacrificial layer (SL) for n-Si/ALD-ZrO2 gate stack followed by the post deposition annealing (PDA) of ZrO2 in argon ambient. The surface morphological studies include atomic force microscopy (AFM) and field emission scanning electron microscopy (FESEM) whereas the thicknesses of the grown films were confirmed by both ellipsometry and FESEM cross-sectional studies. The surface topographical study suggests the r.m.s. roughness of 0.796 nm for nano zirconia film after rapid thermal annealing (RTA). Electrical parameters such as dielectric constant (K), effective oxide thickness (EOT), leakage current density (J), effective oxide charge (Qeff) and series resistance (Rs) were extracted through C-V and I-V measurements and the determined values of K, J, EOT, Qeff and Rs at 100 KHz are 26, 8.75 × 10-9 A/cm2, 2.1 nm, 0.42 × 1013 cm-2 and 4.54 KΩ respectively. The concept of SiON SL has significantly suppressed the existing unacceptable gate leakage current and the interfacial traps owing to appropriate segregation of nitrogen at the interface of SiON/ZrO2. Moreover, PDA of ZrO2 film in argon ambient at 5000 C has reduced the r.m.s. roughness and also contributed to the overall reduction of gate leakage current density, thereby, making ALD-ZrO2/SiON gate stack quite attractive for advanced CMOS devices.