Effect of parameter variations at chip and wafer level on clock skews

Abstract

In this paper, a methodology is proposed to determine clock skews and the performance of clock architectures considering parameter variations in an early stage of technology development. With this methodology, it is possible to separate process-induced clock skew from other effects like imperfect loading. Parameter variations are seen as one of the most important effects influencing chip performance in future. By comparing a 0.45- and a 0.25-/spl mu/m technology, it is shown that in the future, process variations will increase clock skew. The clock skews are determined by measuring the relevant device and metal line parameters as a function of position over chip and wafer. In the past, parameters like IDS, Vth, and resistances could be measured very precisely, although it was difficult to measure low capacitances of single metal lines in the range of femto farad. Thus a new measurement method is used to determine interconnect capacitances extremely precisely. Based on these measurement data, a netlist of a defined clock tree is created by a C-program, and the clock signal delay is simulated. From the delay simulation, we calculate the clock skew for each chip dependent on the parameter variations. Experimental results are separated into a basic random fluctuation part and processing-related contributions on the chip and wafer levels. In addition, the effect of temperature gradients on each chip to the clock skew is simulated. The methodology presented is not restricted to just one clocktree but allows investigation of all kinds of clock distribution circuits. The method has clear advantages with respect to chip area against clocktree realizations on a testchip. No direct and costly measurement of signal delays by voltage contrast methods is required, since all parameters are determined by measurement on the device level.