Abstract
As technologies scale, the impact of process variations to circuit performance and power consumption is increasingly significant. In order to improve the efficiency of statistical circuit optimization, a better understanding of the relationship between circuit variability and process variation is needed. Our work proposes a hierarchical variability model, which addresses both systematic and random variations at wafer, field, die, and device level, and spatial correlation artifacts are captured implicitly. Finally, layout dependent effects are incorporated as an additive component. The model is verified by applying to 90nm ring oscillator measurement data and can be used for variability prediction and optimization.
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