Effect of packaging on interfacial cracking in Cu/ low k Damascene structures

Abstract

In this study, 3D f~te element analysis (FEA) based on a multilevel sub-modeling approach in combination with highresolution moire interferometry was employed to examine the packaging effect on low k interconnect reliability. First, 3D FEA was used to analyze the thermal deformation for a flip chip package and verified with high-resolution moire interferometry. Then multi-level sub-modeling was conducted one level of detail at a time, fust selected a section of the package around solder bumps with highest deformation, then proceeded to the die-solder interface and fmally reached the interconnect level. A crack was introduced along interested interfaces in the interconnect structures and strain energy release rate was calculated by using modified virtual crack closure technique. The FEA results will be compared with that for a stand-alone wafer structure. Both AI and Cu sttuctures were investigated and are compared. Our research results indicate that packaging assembly can significantly impact wafer-level reliability causing interfacial delamination to become a serious reliability concern for Cu/low k structures. Results from studies on the effects of line pitch, ILD materials, and solder bump materials will be reported and discussed. effect of packaging on the en& release rate diving interfacial delamination and its impact on reliability for Cdlow k structures. To investigate this problem, we employed 3D fmite element analysis (FEA) based on a multilevel sub-modeling approach in combmation with high-resolution moire interferometry to examine the packaging effect on low k interconnect reliability. First, 3D FEA was used to analyze the thermal deformation for a flipchip package. Here the modeling results were verified using thermal deformation and strain distributions measured by high-resolution moire interferometry. With a phase-shift technique, the resolution of moue interferometry can reach 26nm per fringe order, which is sufficient to determine strain distributions within a small area in the package accurately. After verifying FEA at the packaging level, multi-level sub-modeling was conducted one level of detail at a time, fmt selected a section of the package around solder bumps with highest deformation, then proceeded to the die-solder interface and finally reached the interconnect level. Simulation details and problems related to sub-modeling will be presented and discussed. In the submodel at the interconnect level, a crack with fvred length was introduced at relevant interfaces. The modified virtual crack