Thermal behavior analysis of lead-free flip-chip ball grid array packages with different underfill material properties

Abstract

Low-k materials have been introduced in the backend interconnects since 90 nm node for advanced microelectronic products in order to reduce the RC delay. However, the fragile low-k layer is very sensitive to the thermal stress induced by the CTE (coefficient of thermal expansion) mismatch at metal/dielectric level as well as at die/package level. In the die/package interaction, the transition to lead-free solders from conventional SnPb eutectic solder degrades the reliability of flip-chip ball grid array (FC-BGA) packages due to its higher reflow temperature. As a result, the underfill layer becomes more critical in protecting both low-K layer and solder bumps from delaminations and cracks. In this study, regular and high resolution Moire interferometry were first employed to measure thermal strains of FC-BGA assemblies with CuSn solder and 2 latest underfill materials, which in turn validate our 3D FEA model. Besides, six kinds of FC-BGA assemblies with different solder alloys and underfill materials were also evaluated by thermal cycling test (TCT). A 3D simulation model using ANSYS™ was created to predict and analyze the fracture susceptibility of the assemblies. The simulation results showed good agreement with TCT experiments. The underfill material with low CTE, moderate modulus, and high Tg (glass transition temperature) is recommended for low-k/FC-BGA packages.