Effect of Oxide Thickness Variation in Sub-micron NMOS Transistor

Abstract

Aggressive scaling of metal oxide semiconductor (MOS) devices have resulted in the use of ultrathin gate oxides, which in turn enhanced the device performance. This work examines different components of tunnelling electron in scaled n-type MOS (NMOS) with ultrathin gate oxides (1.2-2.0 nm). Direct tunnelling currents are focused on the currents between the gate and the channel region in the substrates. The gate direct tunnelling currents are investigated by theoretical modelling and simulation experiments and their effects on the leakage current from those two approaches are compared. The simulation of this project was carried out using Sentaurus TCAD software. A 90 nm NMOS transistor is simulated to investigate the electron tunnelling phenomenon and its effect on the device performance. The 90 nm NMOS device was designed and characterized using Sentaurus TCAD software. In this project, there are two major simulations done using Sentaurus Process and Sentaurus Device. There are four parameters being investigated, which are is oxide thickness (Tox), threshold voltage (VTH), drain voltage (VD) and gate voltage (VG), to obtained result of drain current (ID) and leakage current (IOFF). The simulations data results are listed in the Inspect tools and used to plot graphs to compare between simulation and calculation results. The electrons start tunnelling at the Tox of 1.4 nm with resulting in large IOFF of 2.45×10-9A at VD of 0.5V. The simulation results are found to be almost identical with the theoretical modelling.