Effect of NC pins ESD test on the reliability of integrated circuits with high density BGA package

Abstract

In this study, the failure phenomenon of high-pin-count BGA device ESD test by stressing NC pins was tested and analyzed since NC pin withstands HBM pulse as the signal pin during practical application and experiences new failure mode and mechanism. The effects of NC pins ESD test on the reliability of integrated circuits and the failure mechanism were subsequently investigated via experimental methods. Results show that ESD level identification tests with stressing NC pins exhibit abnormal failure mode compared with typical ESD failure. Meanwhile, a distributed capacitance method (DCM) is proposed to explain the phenomenon and failure mechanism, which is affected by the packaging materials and particular spacing distance between adjacent pins. When the HBM ESD pulse is applied on the NC pin, the signal pin adjacent to NC pin regularly fails due to the existence of distributed capacitance CM + CM(air) and air arc breakdown. The verification experimental tests of failure analysis reveal that the monitored huge and extremely fast current forms through the distributed capacitance coupling and air arc mode.