Effect of LDD structure and channel poly-Si thinning on a gate-all-around TFT (GAT) for SRAM's

Abstract

A lightly doped drain (LDD) structure was used in a gate-all-around TFT (GAT). This suppresses the leakage current much more than the LDD used in a single-gate TFT (SGT), and the current level of the GAT with the LDD is almost the same as that of the single-gate TFT (SGT) with the LDD keeping the GAT's advantage of a high on-current. This is because the LDD effectively relaxes the electric field at the drain edge and reduces the effect of the electric field from the surrounded gate of the GAT. Furthermore, the GAT can suppress individual performance variations. The suppression mechanism of the individual performance variation in a GAT was investigated using a poly-Si TFT simulator. The thinner the channel poly-Si, the smaller the individual performance variation of the TFT. The GAT is more effective in decreasing the individual performance variation for thin channels than the SGT because the GAT can achieve the full depletion of the channel poly-Si with a channel thickness twice as large as the SGT. The GAT is eminently suitable for use in high-density, low-voltage operations, and low-power SRAM's.