Effect of Ge Metal–Insulator–Semiconductor Interfacial Layers on Interface Trap Density near the Conduction Band Edge

Abstract

The interface structures and electrical interface properties near the conduction band edge (CBE) of Ge metal–insulator–semiconductor (MIS) capacitors with Si or GeO2 interfacial layers (ILs) were systematically investigated using physical analysis and the Gray–Brown (GB) method. The accuracy of the values of interface trap density (Dit) obtained by the GB method was confirmed by comparing these with the values obtained by the conductance method. The GB method revealed that Ge MIS capacitors with a Si IL have a large number of interface traps near the CBE, and that the dislocations introduced at a Si IL/Ge interface have an insignificant effect on Dit near CBE. On the other hand, the Dit of the GeO2 IL capacitors was lower by almost one order of magnitude than that of the Si IL capacitors. In addition, the Dit of the GeO2 IL/Ge interface was also reduced by high-temperature oxidation during post metallization annealing. These results indicate that ILs have a strong influence on Dit near the CBE, and that the GeO2 IL and high-temperature oxidation are quite effective in reducing Dit near the CBE.