Effect of Fringing Capacitances on the RF Performance of GaN HEMTs With T-Gates

Abstract

The effects of fringing capacitances on the high-frequency performance of T-gate GaN high-electron mobility transistors (HEMTs) are investigated. Delay time components have been analyzed for gate-recessed InAlN/GaN HEMTs with a total gate length of 40 nm and fT/fmax of 225/250 GHz. It is found that the gate extrinsic capacitance contributes significantly to the parasitic delay-approximately 50% of the total delay in these highly scaled devices. The gate extrinsic capacitance comprises two components: 1) parallel plate capacitances between the T-gate and the surrounding electrodes and 2) the fringing capacitance between the gate stem and the access regions. Detailed study of the gate electrostatics reveals that the later, the fringing capacitance between the T-gate stem and the device access region, ultimately determines the lower limit of the extrinsic capacitance Cext; this minimum Cext can be realized experimentally using a large gate stem height and employing low- k passivation dielectric. Since the corresponding parasitic delay can be expressed as Cext/gm,int, this paper also highlights the importance of maximizing gm,int in ultrascaled HEMTs by adopting strategies to enhance carrier velocity.