Abstract
The Unclamped Inductive Switching (UIS) process is often considered to be the most extreme electro-thermal stress condition a vertical double diffused MOSFET (VDMOS) can encounter. Avalanche energy (EAS) is commonly used to characterize the ability of devices to withstand UIS tests and to assess device reliability. It is found that epitaxial layer has an effect on EAS of VDMOS. Simulations and experimental results have shown that lower resistivity and larger drift region thickness can result in a high EAS for nonpunch-through VDMOS with the same breakdown voltage. A transient additional carrier model is proposed to explain the effect of epitaxial layer. Therefore, in addition to taking effective measures to prevent the parasitic NPN transistor from turning on, it is also very important to select the parameters of epitaxial layer properly to improve the UIS capability of VDMOS.
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